Description
The SCMOS3E is a 5V 0.5µm digital and mixed-signal CMOS technology with a High Temperature capability (200°C) on a standard epitaxial substrate.
This advanced single or double poly, stacked vias, double or triple metal process offers easy embedding optional functions including analog devices as well as embedded non volatile memory blocks (OTP/EPROM up to 125°C).
Thick Last Metal process option improves the capability of lower interconnect resistance and higher current drivability.
The SCMOS3E process technology family is offered with a set of options which can be selected in accordance with the real IC product needs, and efficiently described in a comprehensive Design Kit.
This mixed-signal process is well suited for designing complex ICs, using for example LV CMOS transistors for the core, analog capacitors and resistors for signal amplification and OTP / EPROM memory for the code storage. |
|
Key features
 Epitaxial substrate
Poly Buffer LOCOS isolation
Retrograded wells, N+ and P+ polySi gates
Silicided Gates and Diffusions
NMOS : L=0.5µm, Vt = 0.65V, IDSN=600µA/µm
PMOS : L=0.5µm, Vt= -0.65V, IDSP=350µA/µm
Interpoly linear capacitor (1.25fF/µm²)
Diffusion capacitor (2.70fF/µm²)
High resistive poly resistors (1K or 4Kohms/sq)
N and PHV devices for EPROM operation
(3.0*2.5)µm² FAMOS transistor EPROM Cell
EPROM Data retention >10y @ 85°C
Metal Fuse, Antifuse Diode
Applications
Micro-controllers
Sensor controllers
Industrial automation
Harsh environment applications |