Technology overview

 
    W - series
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    SCMOS - series
   
  Process selection guide
 
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Technology portfolio
  SCMOS1A
    SCMOS3E
    SCMOS3EE
    SCMOS3RT
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SCMOS1A

Description

The SCMOS1A is a mature 5V 0.8µm digital and mixed-signal CMOS technology on a bulk substrate.

This is a double poly, double metal process.

Device portfolio includes:
5V Digital NMOS and PMOS transistors
5V Analog NMOS and PMOS transistors
VPNP and LPNP bipolar transistors
Diffusion and poly resistors
Analog capacitors

  Key features

Bulk substrate
LOCOS isolation ; Twin wells
LDD for NMOS and PMOS
Silicided Poly Gate
Digital NMOS : Lmin=0.8µm, Vt = 0.73V, IDSN=300µA/µm
Digital PMOS : Lmin=1.0µm, Vt= -0.82V, IDSP=160µA/µm
Analog NMOS : Lmin=1.2µm, Vt = 0.58V, IDSN=304µA/µm
Analog PMOS : Lmin=1.2µm, Vt= -0.64V, IDSP=148µA/µm
Interpoly linear capacitor (0.9 fF/µm²)
Poly resistor (30 ohms/sq)
   
For technology choice advice or for design kits and rules access, please contact your regional sales Applications

Micro-controllers
Sensor controllers
Industrial automation